1 of 2 august 13, 2009 ? 2008 integrated device technology, inc. idt and the idt logo are registered trademar ks of integrated device technology, inc. ? device overview the idt tsi384 is a high-performanc e bus bridge that connects the pci express (pcie) protocol to the pci and pci-x bus standards. the tsi384?s pcie interface has superior performance and supports 1, 2, or 4 lanes. this enables the bridge to offer exceptional throughput performance of up to 1 gbps. the device?s pci/x interface can operate up to 133 mhz in pci-x mode, or up to 66 mhz in pci mode. this interface offers designers extensive flexibility by supporting three types of addressing modes: transparent, opaque, and non-transparent. low power consumption the tsi384 has typical power cons umption of 1.3w, and incorporates advanced power management to minimi ze power consumption during operation. in addition to supporting d0, d3 hot, and d3 cold power management modes, the device permits unused pcie lanes to be powered off automatically or by configuration. transparent, non-transparent, and opaque bridging transparent mode operation is avai lable for efficient, flow-through configurations, while non-transparent bridging allows isolation between the tsi384?s pcie and the pci/x dom ains. non-transparent bridging also enables multi-host systems and is used in applications such as storage adapters. opaque mode provides semi -transparent operation for multi- processor configurations and enhanced private device support. high performance the tsi384 incorporates many advanced pcie protocols that increase system performance, incl uding: lane reversal and polarity inversion, end-to-end crc, aspm l0 link state power management, and hot plug. in addition to low-latency operation, the device supports a maximum payload size of up to 512 bytes to allow better throughput effi- ciency. figure 1 tsi384 block diagram features ? general ? pci express to pci/pci-x forward bridge ? transparent, non-transparent, and opaque modes ? low latency ? superior queuing and buffering architecture maximize throughput and minimize latency ? compliant with the following specifications: ? pci express base 1.1 ? pci express pci/pci-x bridge 1.0 ? pci-to-pci bridge architecture 1.2 ? pci local bus 3.0 ? pci-x 2.0 (mode 1 only) ? pci bus power management interface 1.2 pci/x arbiter error handling interrupt handling clocking/ reset eeprom controller power mgmt jtag pci/x interface pcie interface (x4) 80e1000_bk001_01 (tsi384) posted writer buffer posted queue mux logic non- posted buffer non- posted queue downstream d o w n s t r e a m upstream u p s t r e a m posted writer buffer posted queue mux logic non- posted buffer non- posted queue config registers tsi384 ? pcie ? to pci/x bridge product brief
tsi384 evaluation board product brief 2 of 2 august 13, 2009 august 16, 2004august 16, 200 not an offer for sale the information presented herein is subjec t to a non-disclosure agreement and is fo r planning purposes only. nothing contained in this presenta- tion, whether verbal or written, is int ended as, or shall have the effect of, a sale or an offer for sale that creates a contra ctual power of acceptance. corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: email: ssdhelp@idt.com phone: 408-284-8208 document: 80e1000_fb001_07 ? ? pci express ? configurable as 1, 2, or 4 lanes ? 512-byte maximum payload ? advanced error reporting capability ? supports lane reversal and lane polarity inversion ? end-to-end crc check and generation ? up to four outstanding memory reads ? aspm l0s link state power management ? legacy interrupt signaling and msi interrupts ? hot plug support ? pci/pci-x ? 32/64-bit addressing ? 32/64-bit data ? pci-x operation at 50, 66, 100, and 133 mhz ? pci operation at 25, 33, 50, and 66 mhz ? up to eight outstanding memory reads ? 4k read completion buffer ? four external pci/x mast ers supported through internal arbiter ? support for external arbiter ? other ? support for masquerade mode ? jtag ieee 1149.1, 1149.6 ? support for d0, d3 hot, d3 cold power management states ? 1.2v core power supply ? 1.3w typical power consumpti on (x4 pcie to 133-mhz pci-x) ? packaged in 17x17 mm, 256-pin pbga ? package pinout and footprint compatible with plx8114 compatible with plx8114 benefits ? enhances system performance by delivering high throughput and low latency across bus interfaces ? simplifies system design by offering numerous programmable features ? minimizes system power consum ption by providing compre- hensive power management typical applications the tsi384 is suited to applications that need to bridge from pcie to downstream pci-x and pci devices. its flexibility, high performance, small footprint, and low power consumption, make it ideal for a wide range of applications, including: ? storage area network (san, raid hba cards) ? network attached storage, direct attached storage (nas, das) ? line cards and nics ? routers and switches ? motherboards (server, sbc, industrial pc) ? pc adapter cards (communications, graphics, imaging, and multimedia) ? multi-function printers ? digital video recorders figure 2 hba card application 80e1000_ta001_01 pci-x 133 mhz pci-x 133 mhz pcie x4 tsi384 gbe/fc controller gbe/fc controller
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